The general AC transmitted through the AC distribution system of power companies usually are connected to various types of loads that include resistance loads such as incandescent lamps, ovens and the like, and many other types of loads that mostly consist of resistance and induction. Hence on electronic circuits the current phase angle is lagged behind the voltage. In general the total current provided by the power company from generators through the power transmission and distribution lines includes effective current and ineffective current. Due to different rated voltage of different loads, the electrometer at user ends counts on the effective power (KW). However the ineffective power (KVAR) causes line voltage drops and loss. This is a loss to both the user ends and the power company. Hence to regulate power factor is a big issue for providers of user end systems.
The techniques of power factor regulation can be divided into active type and passive type. They aim to reduce power loss, improve power quality, increase the life span of loads and save power expense. Valley filled power factor regulation circuit is one of the techniques adopted on electronic devices that can set a voltage value to regulate power. For instance R.O.C. patent No. M242969 discloses a driving circuit for electronic stabilizers of low resonant waves that mainly includes a power source input and a commutation circuit which consists of D1, D2, D3 and D4, a transformation circuit (valley filled power factor correction circuit) consisting of C2, D5, D6, R7 and C6 to transform AC to DC at almost same voltage, a driving circuit (push-pull inverter circuit) consisting of two complimentary high voltage transistors (preferably MOSFET) to transform DC to a high frequency square wave, and a voltage division circuit to generate an one half power voltage that has an output end connecting to one end of a lamp. Its features include the driving circuit having a resistor switch R3 to provide a small bias voltage to activate an inductor. The resistor switch is coupled with a capacitor C3 to isolate DC from entering the inductor. The resistor switch further is coupled with DZ1 to limit the bias voltage amplitude of the transistors within the range of 12V. The resistor switch also is connected to a LC resonant circuit consisting of C4 and an inductor to transform oscillating square waves to sinusoidal waves. The resistor switch further is connected to a C1 to improve wave filtering and enhance CF value. The resistor switch also is connected to one C to isolate DC portion so that the load is driven by AC. The resistor switch further is connected to C5 and R4 to improve the surge of the square waves.
Other reference of the valley filled power factor regulation circuit can be found in R.O.C. patent Nos. M290932 and R.O.C. patent publication Nos. 519854, and U.S. Pat. Nos. 7,061,781, 6,909,622, 5,517,086, 6,667,586 and 6,297,613.
The valley filled power factor regulation circuits in the aforesaid techniques mostly have a transistor switch at the rear end to split power signals. The transistor switch in practice has a duty voltage value which is the lowest voltage when the transistor switch is in an operating condition. When an electronic device equipped with a valley filled power factor regulation circuit is in an operating condition, if the signal transmitted to the transistor switch has a voltage value lower than the duty voltage of the transistor, the transistor cannot enter the operating condition due to not sufficient voltage. Then the power of signals transmitted to the transistor switch will accumulate on the input end of the transistor switch. When the accumulated power reaches the limit of the transistor switch, the transistor switch will be damaged or pierced. Hence how to prevent accumulation of low voltage power to damage or pierce the transistor switch is a big issue pending to be resolved in the industry.